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PIC18F/LF1XK50

DS41350E-page 24

Preliminary

2010 Microchip Technology Inc.

TABLE 2-2:

EXAMPLES OF DELAYS DUE TO CLOCK SWITCHING

2.9

4x Phase Lock Loop Frequency

Multiplier

A Phase Locked Loop (PLL) circuit is provided as an

option for users who wish to use a lower-frequency

external oscillator or to operate at 32 MHz with the

HFINTOSC. The PLL is designed for an input

frequency from 4 MHz to 12 MHz. The PLL multiplies

its input frequency by a factor of four when the PLL is

enabled. This may be useful for customers who are

concerned with EMI, due to high-frequency crystals.

Two bits control the PLL: the PLLEN bit of the

CONFIG1H Configuration register and the SPLLEN bit

of the OSCTUNE register. The PLL is enabled when

the PLLEN bit is set and it is under software control

when the PLLEN bit is cleared.

TABLE 2-3:

PLL CONFIGURATION

2.9.1

32 MHZ INTERNAL OSCILLATOR

FREQUENCY SELECTION

The Internal Oscillator Block can be used with the 4X

PLL associated with the External Oscillator Block to

produce a 32 MHz internal system clock source. The

following settings are required to use the 32 MHz inter-

nal clock source:

The FOSC bits in CONFIG1H must be set to use

the INTOSC source as the device system clock

(FOSC<3:0> = 1000 or 1001).

The SCS bits in the OSCCON register must be

cleared to use the clock determined by

FOSC<3:0> in CONFIG1H (SCS<1:0> = 00).

The IRCF bits in the OSCCON register must be

set to the 8 MHz HFINTOSC set to use

(IRCF<2:0> = 110).

The SPLLEN bit in the OSCTUNE register must

be set to enable the 4xPLL, or the PLLEN bit of

CONFIG1H must be progr mmed to a ‘1’.

The 4xPLL is not available for use with the internal

oscillator when the SCS bits of the OSCCON register

are set to ‘1x’. The SCS bits must be set to ‘00’ to use

the 4xPLL with the internal oscillator.

2.10

CPU Clock Divider

The CPU Clock Divider allows the system clock to run

at a slower speed than the Low/Full Speed USB

module clock while sharing the same clock source.

Only the oscillator defined by the settings of the FOSC

bits of the CONFIG1H Configuration register may be

used with the CPU Clock Divider. The CPU Clock

Divider is controlled by the CPUDIV bits of the

CONFIG1L Configuration register. Setting the CPUDIV

bits will set the system clock to:

Equal the clock speed of the USB module

Half the clock speed of the USB module

One third the clock speed of the USB module

One fourth the clock speed of the USB module

For more information on the CPU Clock Divider, see

Figure 2-1 and Register 24-1 CONFIG1L.

Switch From

Switch To

Oscillator Delay

Sleep/POR

LFINTOSC

HFINTOSC

Oscillator Warm-up Delay (TWARM)

Sleep/POR

LP, XT, HS

1024 clock cycles

Sleep/POR

EC, RC

8 clock cycles

PLLEN

SPLLEN

PLL Status

PLL enabled

PLL disabled

Note:

When using the PLLEN bit of CONFIG1H,

the 4xPLL cannot be disabled by software

and the 8 MHz HFINTOSC option will no

longer be available.

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